The present invention relates to a data processor and a graphic processor using the unified memory architecture using a part of a main memory of a CPU for processing data as a frame buffer memory for image display.
A conventional data processor using unified memory architecture is described in Japanese Patent Application Laid-Open 4-84192.
In this processor, a memory for buffering data to be transferred between a CPU and a main memory once is provided so as to prevent the main memory from being occupied by access by the CPU, and a display controller provided for controlling display on a display unit reserves a period for reading data from the main memory for display.
As an example of a conventional data processor using unified memory architecture, an apparatus which is structured so as to use a part of a memory as a Z buffer and a texture memory necessary for three-dimensional graphics in addition to a frame memory and to allow a rendering processor or a geometric processor for processing three-dimensional graphics to access it is also known.
Furthermore, a processor for processing graphics at high speed (Quoted Example 1) is described in xe2x80x9cThree-dimensional CG Drawing LSI-300000 Polygons/Second Realized by Personal Computer-(Nikkei Electronics, No. 640, Jul. 17, 1995, pp 109-120)xe2x80x9d. This processor is provided with three kinds of memories, such as a texture memory, a frame buffer memory and a local memory, as dedicated processor memories. This architecture is advantageous in respect of improvement of the performance, though it is not suited to a compact and inexpensive apparatus, such as an individual portable device, because a plurality of memories are necessary. On the other hand, an example in which graphic information is unified and the number of memories can be reduced compared with Quoted Example 1 is disclosed in Japanese Patent Application Laid-Open 5-257793 (Quoted Example 2). This graphic system has a CPU program, texture data, and a frame buffer which are unified in a main memory of a CPU.
According to each of the aforementioned processor systems, there is a problem in that access to the main memory by the CPU is forced to wait due to access to the main memory which is being executed by the display controller or the rendering processor, and so the processing performance of the whole processor is degraded. Furthermore, the period for which the access to the main memory by the CPU is forced to wait depends on the access executed by the display controller or the rendering processor, so that the period for which the access to the main memory by the CPU is forced to wait cannot be confirmed beforehand. As a result, in these systems, it is impossible to guarantee the degradation of the processing performance of the whole processor by less than a fixed limit.
Furthermore, in the aforementioned processor systems, the assumption has been made that the data processor has a memory system which is sufficiently quick so that the access capacity of the memory is several hundreds MB/s and the display data reading time can be reserved sufficiently. This assumption requires an expensive memory system and disturbs miniaturization and cost reduction.
Even in the constitution of Quoted Example 2, if the access capacity of the memory is reduced by use of an inexpensive memory system, adjustment with drawing other than display and CPU access is necessary so as to reserve the display data reading time necessary for moving images. The write access time from the CPU varies with the data amount, though the data amount for each time for high-speed graphics increases and the access time for each screen also increases.
As a result, in the memory unified type, display access is given priority. However, even if an access request for reading drawing data (hereinafter called display access) is issued from the graphic memory, when another access is being executed by the CPU or others, the access request is forced to wait until it ends and if the data of the display buffer becomes empty during the period of time, the moving image display screen is disturbed. Therefore, a sufficient display access time is reserved, and the data storage amount of the display buffer is increased, and the quality of moving images is maintained. However, in the conventional display access priority system, the access efficiency of the graphics memory reduces, so that the processing of high-speed graphics by the CPU becomes difficult.
Generally, the CPU has a built-in cache memory for transferring output data and the memory access timing varies with the cache system. For example, the write through system transfers only one word. On the other hand, the copy back system for transferring a plurality of words continuously can transfer drawing procedure information (hereinafter called a drawing command) together, so that the access time can be shortened. Nevertheless, in the write through system in which the access time is long, a sufficient display access time is reserved. Namely, the difference in the cache system is not taken into account, so that the access efficiency of the memory reduces and high speed graphics display executable by the copy back system is sacrificed.
An object of the present invention is to provide a data processor using unified memory architecture for reducing degradation of the processing performance of the whole processor.
Another object of the present invention is to provide a data processor, when a graphics memory to be accessed from both a CPU and a graphics processor is used, for optimizing the continuous time for one display access depending on the cache system of the CPU, for increasing the access efficiency of the memory, and for realizing high speed graphics display and the graphics processor.
To accomplish the above first object, the present invention provides a data processor which has, for example, a CPU, a main memory, and a display controller for controlling display on a display unit and uses a part of the storage area of the main memory as a frame buffer for storing display data which is read by the display controller and displayed on the display unit, wherein the data processor has a memory controller for connecting to a memory bus connected to the main memory, a CPU bus connected to the CPU, and a local bus connected to the display controller, relaying the memory access sequence of the CPU to the main memory between the CPU bus and the memory bus, and relaying the memory access sequence of the display controller to the main memory between the local bus and the memory bus, and the memory controller gives priority to relaying of the memory access sequence between the CPU bus and the memory bus over relaying of the memory access sequence between the local bus and the memory bus, and even if a memory access by the CPU to the main memory occurs at a maximum frequency restricted by the throughput of the CPU bus, the throughput of the memory bus is set to a value larger than the throughput of the CPU bus so that the memory access frequency of the display controller to the main memory which is necessary for display on the display unit is reserved.
By use of such a constitution, when relaying of the memory access sequence between the CPU bus and the memory bus is given priority over relaying of the memory access sequence between the local bus and the memory bus, it can be guaranteed to prevent performance degradation due to waiting of the CPU for access to the main memory and to allow the display controller to effect a display without trouble by setting the throughputs of the CPU bus and memory bus as mentioned above.
Furthermore, to accomplish the above first object, the present invention provides a data processor which has, for example, a CPU, a main memory, and a display controller for controlling display on a display unit and uses a part of the storage area of the main memory as a frame buffer for storing display data which is read by the display controller and displayed on the display unit, wherein the data processor has a memory controller for connecting to a memory bus connected to the main memory, a CPU bus connected to the CPU, and a local bus connected to the display controller, relaying the memory access sequence of the CPU to the main memory between the CPU bus and the memory bus, and relaying the memory access sequence of the display controller to the main memory between the local bus and the memory bus and the memory controller has a means for freezing execution of the memory access sequence of the display controller to the main memory when the memory access sequence of the CPU to the main memory starts on the CPU bus during relaying of the memory access sequence of the display controller to the memory bus, releasing the freezing of execution of the memory access sequence of the display controller to the main memory after the memory access sequence of the CPU to the main memory ends, and executing the unexecuted portion of the memory access sequence.
By use of such a constitution, when access by the CPU to the main memory occurs, by freezing the access by the display controller, waiting by the CPU for access to the main memory can be guaranteed less than the cycle necessary for the freezing process and by releasing the freezing of the stopped access by the display controller to the main memory, the access can be restarted from the point of time when the freezing is released. Therefore, the degradation of the access efficiency of the display controller to the main memory can be reduced.
To accomplish the above second object, the data processor of the present invention has a CPU for generating drawing procedure information (drawing command) comprising the kind of graphic diagrams to be displayed and top parameters, a memory for storing the aforementioned drawing procedure written (write access) from the CPU and drawing data (bit map information) outputted to a display unit, and a graphics processor for executing drawing access to the drawing procedure information, storing drawing data in the memory, and further executing display and reading (display access) for outputting the drawing data to the display unit, and furthermore the graphics processor changes the display and reading timing for the memory according to the cache system of the cache memory for transferring data to the memory provided in the CPU.
The graphics processor is given cache system information indicating whether the cache system is a system for transferring a plurality of words continuously to the memory or a system for transferring each word individually from the CPU, and the continuous time of one display and reading in the former case is made shorter than that in the latter case.
To accomplish the above object, the graphics processor of the present invention executes drawing access for generating bit map information and display access for displaying display data on a display unit to a graphics memory having a storage area for drawing procedure information (drawing command) comprising the kind of graphic diagrams to be displayed and top parameters and an area for storing the bit map information to be outputted to the display unit and furthermore transfer system information indicating whether the write access of the drawing procedure information to the graphics memory is a system for transferring data of a plurality of words at continuous addresses or a system for transferring data for each word is set and the continuous time of one display access in the former case is made shorter than that in the latter case.
Furthermore, the graphics processor has a drawing unit for executing a drawing access, a display controller for executing a display access, an interface means for receiving data transferred from the CPU and executing the write access, and a memory controller means for receiving those memory access requests and controlling them so as to give priority to the display access, and the transfer system information is set by the cache system of the CPU for transferring the drawing procedure information, and when the cache system is a copy back system, the continuous time of one display access is made shorter than that in the write through system.
Furthermore, the graphics processor has a display butter br temporanly stonng the bit map information which is read from the graphics memory by the display access and outputting it at the timing of the display unit, and the number of continuous words by one display access mentioned above is set as a maximum value of the number of held data of the display buffer, and the timing of request issue of the display access is set as a threshold value less than the number of held data, and the maximum value and threshold value vary with the transfer system information.
According to the present invention having the aforementioned constitution, when the CPU is a copy back system, data is written into the graphics memory by the CPU at continuous addresses, so that the write access time for the same data amount is made shorter. Therefore, the spare time for reserving the priority of the display access may be reduced by the shortened time and the time of one write access and the time of display access can be shortened as a whole compared with the write through system, so that the access efficiency of the memory is increased and graphics can be processed at high speed. In other words, following write access of drawing data by the high-speed copy back system on the CPU side, a high-speed drawing process can be performed.